a TAPR Modular Scientific Software Defined Radio Project


Data Engine

Project Leader: Scotty WA2DFI

DCC2020 TangerineSDR Data Engine Talk
DCC2020 TangerineSDR Data Engine Slides


DataEngine Document
DataEngine Protocol V 1.4

DataEngine Schematic
DataEngine Top Layout
DataEngine Bottom Layout

Prototype Adapter Board for MAX10 Development Board

DataEngine Adaptor Schematic
DataEngine Adaptor Top Layout
DataEngine Adaptor Bottom Layout


Max10 Links
How to Begin a Simple FPGA Design
MAX 10 FPGA – Booting Nios II Processor (Part 1)
MAX 10 FPGA - Booting Nios II Processor (Part 2)
MAX 10 FPGA User Flash Memory
How to communicate between a host PC to USB UART
MAX10 Remote System Update Part1
MAX10 Remote System Update Part 2
MAX10 Remote System Update Part 3
Remote System Upgrade in Intel® MAX® 10 Devices
Quartus Programmer Links
Using the Intel® Quartus® Prime Standard Edition Software: An Introduction
Verilog Example and Gate Level Simulation with Quartus Prime Lite Edition 20.1 and ModelSim
Nios II Processor System Links
The Nios® II Processor: Introduction to Developing Software
The Nios® II Processor: Booting
The Nios® II Processor: Booting (Part 2)
The Nios® II Processor: Hardware Abstraction Layer
MAX 10 Document Links
Intel MAX 10 FPGA Support Documents
Using the NicheStack TCP/IP Stack - Nios II Edition Tutorial
Nios II Ethernet Simple Socket Server on MAX10 FPGA Development Kit



Allied Organizations

HamSci Personal Space Weather Station

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